A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for 128 × 8 64-QAM Massive MIMO in 65 nm CMOS




Published Date:2018-05


Abstract—The minimum-mean-square error (MMSE) plays a significant role in the signal detection process of massive multipleinput- multiple-output (MIMO) systems. Matrix inversion, which is the major part of calculating the MMSE, suffers from high computing loads and low parallelism, especially in massive MIMO systems; as such, hardware implementation is difficult. This paper proposes a user-level parallelism-based fully pipelined very large-scale integration (VLSI) architecture of an MMSE detector for an uplink 128 × 8 64-QAM massive MIMO system. First, a diagonal-based systolic array with single-sided input is adopted; this array eliminates the throughput limitation. Second, a weighted Jacobi-iteration-based architecture is proposed to iteratively achieve matrix inversion, thereby reducing the computational load and exploiting the potential parallelism of the matrix inversion. Third, an approximated architecture is proposed to compute the log-likelihood ratio. This architecture is verified on an FPGA and fabricated onto a 2.57 mm2 silicon with TSMC 65 nm CMOS technology, thereby achieving a 1.02 Gbps data rate at 680 MHz while dissipating 646 mW. The results indicate an energy efficiency of 1.58 Gbps/W and an area efficiency of 0.40 Gbps/mm2, which are 2.93× and 2.86× that of stateof- the-art similar designs with CMOS technology, respectively.

This entry was posted in Publications and tagged . Bookmark the permalink.

Leave a Reply